Data communication is an important function of many integrated circuits. In high speed data communication, automatic gain control (AGC) on the receiver side is needed to adjust the received signal magnitude to achieve an adequate input swing for the decision logic or data slicer. In most analog based receiver designs, the gain is adjusted such that the averaged peak signal magnitude at the sampling point (commonly referred as h(0) or vpeak) reaches a pre-defined target. However, such an adjustment of the gain could lead to significant circuit nonlinearity when the maximum signal is much larger than the averaged peak signal. When an equalization technique such as feedforward equalization (FFE) or decision feedback equalization (DFE) is used, which is almost ubiquitously required for high speed communication links (e.g. greater than 10 Gbps), this nonlinearity will deteriorate eye margin and hence hurt bit error rate (BER). Alternatively, in many ADC based receiver designs, the gain is adjusted by monitoring the ADC code clipping rate. The clipping rate, however, can be strongly influenced by channel ISI profile, noise amount and crosstalk signature, hence making the adjustment less robust for different systems.
Accordingly, improved circuits for and methods of enabling the adaptation of an automatic gain control circuit when receiving data in an integrated circuit are beneficial.